The present invention relates to computer systems, and, more particularly, to a computer system having a bus bridge with a relatively low number of external terminals.
When a computer system is powered on or reset, computer instructions are executed that are part of a basic input/output system (xe2x80x9cBIOSxe2x80x9d) program. The BIOS program is normally in the form of firmware routines stored in a read only memory (xe2x80x9cROMxe2x80x9d), which may or may not be a programmable read only memory (xe2x80x9cPROMxe2x80x9d). The processor may execute the BIOS program directly from the BIOS ROM. However, the BIOS program is usually transferred from the BIOS ROM to system memory, such as dynamic random access memory (xe2x80x9cDRAMxe2x80x9d), in a process known as xe2x80x9cBIOS shadowing.xe2x80x9d Following transfer of the BIOS program to. system memory, the processor is initialized and then executes initialization routines, or bootstrap routines, that are part of the BIOS program from the system memory. This entire process, including any shadowing of the firmware routines from the ROM to the system memory, is known as xe2x80x9cbootingxe2x80x9d the computer system
If the processor executes the BIOS program directly from the BIOS ROM, it must repeatedly apply an address to the ROM and then couple an instruction to the processor that is stored at the address in the ROM. If the BIOS program is shadowed, the processor repeatedly fetches and executes instructions for transferring the BIOS program from the BIOS ROM, as well as the BIOS program itself, in a multi-step process. In either case, the BIOS program instructions are transferred over a relatively low-speed bus through a bus bridge to a processor bus that is connected to the processor.
A variety of configurations may be used in a computer system to couple a BIOS ROM to a processor. Examples of such systems are illustrated in FIGS. 1 and 2. With reference to FIG. 1, a computer system 10 includes a processor 14, such as an Intel(copyright) Pentium(copyright) processor or Pentium II(copyright) processor, although other processor may, of course, be used. For example, the processor 14 may be any microprocessor, digital signal processor, micro controller, etc. The processor 14 is coupled to a processor bus 16 which includes data, control, and address buses (not shown) that provide a communication path between the processor 14 and other devices, as explained below. One device with which the processor 14 communicates is a cache memory device 18, typically cache static random access memory (xe2x80x9cSRAMxe2x80x9d), which is also coupled to the processor bus 16. As is well known in the art, the cache memory device 18 is generally used for the high speed storage of instructions that are frequently executed by the processor 14, as well as for data that are frequently used by the processor 14.
Also coupled to the processor bus 16 is a system controller 20. The system controller 20 performs two basic functions. First, the system controller 20 interfaces the processor 14 with a system memory 22, which is generally a dynamic random access memory (xe2x80x9cDRAMxe2x80x9d). More specifically, the system memory 22 may be an asynchronous DRAM, a synchronous DRAM (xe2x80x9cSDRAMxe2x80x9d), a video or graphics DRAM, a packetized DRAM, such as a synchronous link DRAM (xe2x80x9cSLDRAMxe2x80x9d), or any other memory device. The system controller 20 includes a DRAM controller 24, which interfaces the processor 14 to the system memory 24 to allow the processor 14 to write data to and read data from the system memory 22. Basically, the system controller 20 performs this function by receiving and sending data to the processor 14 (although the data may bypass the system controller 20 by being coupled directly to the processor bus 16), receives addresses from the processor 14, and receives high level command and control signals from the processor 14. In response, the system controller 20 couples the data to and from the system memory 22 via a data bus 32, generates separate row and column addresses and sequentially applies them to the memory device via an internal address bus 34, and generates and applies to the system memory 22 lower level command signals via a control bus 36.
The second function performed by the system controller 20 is to interface the processor bus 16 to a peripheral I/O bus, such as a Peripheral Component Interconnect (xe2x80x9cPCIxe2x80x9d) bus 40. The PCI bus 40, in turn, is coupled to a conventional PCI-ISA bus bridge 42 and a conventional VGA controller 44 driving a conventional display 46. The PCI bus 40 may also be connected to other peripheral devices (not shown) in a manner well known to one skilled in the art. The PCI-ISA bus bridge 42 may also include a disk drive controller, such as an Intelligent Drive Electronics (xe2x80x9cIDExe2x80x9d) controller 48, which controls the operation of an IDE disk drive 50 in a conventional manner.
The PCI bus 40 is a relatively high speed peripheral I/O bus. Many peripheral devices are adapted to interface with a relatively slow speed peripheral I/O bus, known as an industry standard architecture (xe2x80x9cISAxe2x80x9d) bus. The computer system 10 illustrated in FIG. 1 includes an ISA bus 60 that may be coupled to such I/O devices as a Keyboard Controller, Real Time Clock, and Serial and Parallel Ports, all of which are collectively designated by reference number 62. The ISA bus 60 may also be coupled to a BIOS ROM 64 as well as other I/O devices (not shown) as is well known in the art. The BIOS ROM 64 stores the BIOS program, which, as explained above, is executed by the processor 14 at boot-up, either directly or after being transferred to the system memory 22 if the BIOS is shadowed.
Although the BIOS ROM 64 is shown in the computer system 10 of FIG. 1 coupled to the ISA bus 60, it will be understood that it has conventionally been coupled to other components or buses, including the PCI bus 40, the IDE controller 48 within the PCI-ISA bridge 42, and a controller within the system controller 20. For example, an alternative example of a conventional computer system 70 shown in FIG. 2 includes many of the same components used in the computer system 10 of FIG. 1. Therefore, in the interest of brevity, an explanation of their structure and operation will not the repeated. The system 70 uses a system controller 80 that includes not only a DRAM controller 82 and a PCI bus controller 84, but also an accelerated graphics processor (xe2x80x9cAGPxe2x80x9d) controller 86 and an IDE controller 88. The computer system 70 shown in FIG. 2 thus reflects the trend in computer architecture to couple as many components as possible to the system controller 80. The AGP controller 86 is coupled to an accelerated graphics processor 90 which is, in turn, coupled to a display 94. The IDE controller 88 is coupled through an IDE data bus 96 and an IDE control bus 98 (sometimes known as PC AT Attached (xe2x80x9cATAxe2x80x9d) buses) to a BIOS ROM 100 as well as to a pair of IDE devices 102, 104, such as disk drives. Not shown in FIG. 2, as will be apparent to one skilled in the art, is circuitry for multiplexing the data bus 96 between an address bus port of the BIOS ROM 100 and a data bus port of the BIOS ROM 100 since the IDE, or ATA, bus does not include an extensive address bus. Instead, the IDE bus includes only 4 address bits.
In operation, the system controller 80 is used to interface the processor with all of the other components of the computer system 70 except the cache memory device 18, i.e., the system memory 22, the PCI bus 40, the accelerated graphics processor 90, and the BIOS ROM 100 and IDE devices 102, 104. When a BIOS instruction is to be transferred, the IDE controller 88 outputs the address of the instruction""s storage location on the IDE data bus 96, and the BIOS ROM then outputs the instruction which is coupled to the IDE controller 88 through the IDE data bus 96.
One problem with the computer system 10 illustrated in FIGS. 1, and particularly the computer system 70 illustrated in FIG. 2, is a proliferation of external terminals that the system controllers 20, 80 and the PCI-ISA bridge 42 must have to interface with all of the components to which they are connected. Increasing the number of terminals on an integrated circuit, such as a bus bridge, increases the cost of packaging the integrated circuit, increases the size of the integrated circuit package, increases the cost and complexity of mounting the integrated circuit on a circuit board, and increases the likelihood all of a faulty interconnection. It is therefore desirable to minimize the number of external terminals on an integrated circuit, such as a bus bridge. Although this problem exists to some degree with many integrated circuits in a computer system, it is particularly serious for system controllers and bus bridges since they generally have more external terminals than other integrated circuits in computer systems.
The problems resulting from the proliferation of external terminals are exacerbated by two trends in computer system architecture. First, the sizes of data buses continue to increase to support the faster transfer of data, and the sizes of address buses continue to increase to allow addressing larger capacity system memories. As the size of these buses have increased, the number of terminals that the system controller or bus bridge must have to interface with these buses had correspondingly increased. For example, data buses have grown from 16 data bits, to 32 data bits to currently 64 data bits. Even larger data buses can be expected in the future. Second, as mentioned above, there has been a tendency to relocate the interface with peripheral devices closer to the processor to decrease the time required to access the peripheral devices. This trend is illustrated by comparing the computer system 10 of FIG. 1 with the computer system 70 of FIG. 2. However, as this trend continues, the system controller must interface with additional buses, as also exemplified by the computer system 70 of FIG. 2. Both of these trends have increased the number of external terminals that the system controller must include and, and as a result, have increased the resulting problems.
There is therefore a need to reduce the number of external terminals on the system controllers of computer systems despite industry trends tending to increase the number of such external terminals.
A computer system includes a processor communicating though a processor bus, a system read/write memory communicating though a system memory bus, and an addressable device, such as a read only memory, capable of outputting data responsive to an address. The addressable device communicates though a plurality of buses at least one of which is coupled to the processor bus. A bus bridge or system controller is coupled to the processor bus, the system memory bus, and at least one of the buses of the addressable device. The bus bridge is structured to permit the processor to communicate with each of the system read/write memory, and the addressable device.